Hello All,
After spending some time off working on other projects (that will be posted here soon) I was able to revisit the RiSC-16 and implement a simple CPU in Verilog. This implementation is not pipelined, that will be the next endeavor. I also have an Altera DE-0 in the mail that I will be using for upcoming projects. Anyways, below is the verilog code used to build a simple RiSC-16 CPU.
// Define statements for instructions `define ADD 3'b000 `define ADDI 3'b001 `define NAND 3'b010 `define LUI 3'b011 `define SW 3'b100 `define LW 3'b101 `define BNE 3'b110 `define JALR 3'b111 //Define Statements for instruction formats `define OP 15:13 `define RA 12:10 `define RB 9:7 `define RC 2:0 `define UI 9:0 `define SI 6:0 `define ZERO 16'd0 `define HALT 32'hE071 module RiSC16(clk); input clk; reg [15:0] rf[0:7]; // Each of the registers reg [15:0] pc; // Program counter reg [15:0] m[0:200]; // Memorty, 64K 16 bit spaces reg [15:0] instr; reg [8:0] j; reg inc; //Used to detect when the PC has been incremented! initial begin inc = 0; pc = 0; rf[0] = `ZERO; rf[1] = `ZERO; rf[2] = `ZERO; rf[3] = `ZERO; rf[4] = `ZERO; rf[5] = `ZERO; rf[6] = `ZERO; rf[7] = `ZERO; for (j=0; j<200; j= j+1) begin m[j] = 16'd0; end end always @(negedge clk) begin rf[0] = `ZERO; // The zero register is always zero by convention end always @(posedge clk) begin instr = m[pc]; inc = 0; case(instr[`OP]) `ADD : rf[instr[`RA]] <= rf[instr[`RB]]+rf[instr[`RC]]; `ADDI : rf[instr[`RA]] <= rf[instr[`RB]]+instr[`SI]; `NAND : rf[instr[`RA]] <= !(rf[instr[`RB]]&&rf[instr[`RC]]); `LUI : rf[instr[`RA]] <= (32'hFFC0 && rf[instr[`UI]]); `SW : m[rf[instr[`RB]]+instr[`SI]] <= rf[instr[`RA]]; `LW : rf[instr[`RA]] <= m[rf[instr[`RB]]+instr[`SI]]; `BNE : begin if(rf[instr[`RA]]!=rf[instr[`RB]]) begin pc <=instr[`SI]; inc = 1; end end `JALR : begin pc<=rf[instr[`RB]]; rf[instr[`RA]]<=(pc+1); end endcase if(inc==0) begin pc <= pc+1; end end endmodule //This is code that was given in the assignment module top (); reg clk; RiSC16 cpu(clk); integer j; initial begin #1 $readmemh("test.dat",cpu.m); #1000 $finish; end always begin #5 clk = 0; #5 clk = 1; //m[rf[instr[`RB]]+rf[instr[`SI]]] // $display("pc: %h", cpu.pc); // $display("`RA: %h",cpu.instr[`RB]); // $display("`RB: %h",cpu.instr[`RB]); // $display("`SI: %h",cpu.instr[`SI]); // $display("OP: %h",cpu.instr[`OP]); $display("-----------------------------"); $display("Instruction - %h",cpu.instr); $display(" mem[10] - %h", cpu.m[10]); $display(" r0 - %h", cpu.rf[0]); $display(" r1 - %h", cpu.rf[1]); $display(" r2 - %h", cpu.rf[2]); $display(" r3 - %h", cpu.rf[3]); $display(" r4 - %h", cpu.rf[4]); $display(" r5 - %h", cpu.rf[5]); $display(" r6 - %h", cpu.rf[6]); $display(" r7 - %h", cpu.rf[7]); end endmodule